Transistors fabricated on Silicon-On-Insulator (SOI) substrate have significant advantages such as higher speed, lower power and higher density than on bulk silicon wafer substrate. The SOI substrate typically consists of a thin surface layer of single crystal silicon on an insulator layer on a bulk silicon wafer. The thin surface silicon layer is the silicon channel of the transistor, and the insulator layer, usually made of silicon dioxide, is commonly referred to as the buried oxide.
SOI wafers improve the transistor performance by reducing the operating silicon volume and by isolating the transistors. The thin surface silicon layer limits the volume of silicon that needs to be charged to switch the transistor on and off, and therefore reduces the parasitic capacitance of the transistor and increases the switching speed. The insulator layer isolates the transistor from its neighbors, and therefore reduces the leakage current and allows the transistor to operate at lower supply voltages and thus the transistors can be smaller and more densely packed.
SOI substrates are typically fabricated by oxygen implantation into a single crystal silicon wafer. Recently, a SOI wafer bonding method is introduced in which a wafer having a single crystal silicon surface is tightly joined with a wafer having an insulator surface. The composite substrate is then polished or etched until a single crystal silicon thin film remains on the insulating film.
The SOI wafer bonding method enables a new class of SOI substrate, called SSOI (Strained Silicon-On-Insulator) substrate where the single crystal silicon layer disposed on the insulator substrate is under strained. Transistor devices fabricated on a strained single crystal silicon substrate have been experimentally demonstrated to have enhanced device performance compared to devices fabricated on unstrained silicon substrates. The potential performance improvements are due to the electron and hole mobility enhancements by the introduction of strain-induced band modification of the device channel, resulting in increased device drive current and transconductance, high circuit speed, low operation voltage and low power consumption.
The strained silicon layer is the result of stress imposed on a silicon layer deposited on a seed layer whose lattice constant is different from that of silicon. For larger/smaller seed layer lattice constant, the silicon layer will try to extend/contract itself to match it, and therefore experiences biaxial tensile/compressive stress and forms a tensile/compressive strained silicon layer. For example, the lattice constant of germanium is about 4.2 percent greater than that of silicon, and the lattice constant of a silicon-germanium alloy is linear with respect to its germanium concentration. As a result, the lattice constant of a SiGe alloy containing 50% germanium is about 1.02 times greater than the lattice constant of silicon. By depositing an epitaxial silicon layer on a relaxed silicon germanium (SiGe) layer, the epitaxial silicon layer will be under tensile strain and becomes a single crystal strained silicon layer, suitable for transistor device strained channel.
Similar to the SOI bonding technique, the fabrication of SSOI substrate in general comprises the following steps:                Preparation of thin strained silicon layer on a silicon substrate by depositing a strained-induced seed layer such as SiGe, followed by a strained silicon layer.        Hydrogen split implantation onto the silicon substrate underneath the strained silicon layer to generate a region of subsurface microcracks.        Substrate bonding process of the silicon substrate to an insulator substrate to create a composite substrate.        Thermal anneal to grow the subsurface microcracks, which separate the strained silicon layer portion along the hydrogen implantation region from the silicon substrate.        Surface polishing the SSOI substrate to achieve a strained silicon layer smooth surface on the insulator substrate.        
A major drawback of the prior art SSOI process is its potential damage to the strained silicon layer due to the closeness of the cleave plane to the strained silicon layer. The hydrogen split implantation dose of about 4×1016 should generate sufficient defects and dislocations in the silicon substrate. Although this damage is mostly near the projected range, some defects and dislocations can propagate into the strained silicon layer. For plasma immersion ion implantation process, which is an alternative for low cost hydrogen implantation, the damage zone is much broader and thus the strained silicon is more affected. The extension of defects and dislocations can go very far into the same matrix material, reaching the strained silicon layer in the absence of any interface or boundary.
Also, in the prior art methods to produce strained silicon layer, conventional practice has been to grow a uniform or graded SiGe layer to a few microns to generate sufficient stress where misfit dislocations start to form through the SiGe layer to relieve the stress and relax the SiGe layer. However, there are several disadvantages to the growth of the thick SiGe layer. First, with a few micrometers SiGe, integration is not easy and not cost effective. Second, the high defect density in this thick SiGe layer, about to 104 to 107 cm−2, could significantly affect the device performance. More importantly, the thickness of this SiGe layer cannot be easily reduced because of the need for a high degree of relaxation for strained silicon applications.
Other disadvantage is the high stress involved in the prior art SSOI fabrication process, from the long low-temperature anneal to enhance the bonding strength, to the high temperature anneal for splitting the silicon layer, and local non-uniform heating. The formation of blisters and craters due to high stress relieve in the surface of a silicon wafer implanted with hydrogen ions after annealing is well-known and remains one of the major issues in SSOI fabrication process. One of the methods to prevent stress built up is to pattern the strained silicon layer, for example, see co-pending applications by the same first inventor and common assignee, entitled “Methods of making relaxed silicon-germanium on insulator via layer transfer”, and “Method of making relaxed silicon-germanium on insulator via layer transfer with stress reduction” hereby incorporated by reference.